Method for fabricating a memory cell having a MOS transistor

摘要

A memory cell has a vertical MOS transistor which contains a first electrically insulated gate electrode and a second gate electrode. The second gate electrode is partially disposed in a trench whose sidewall is adjoined by the MOS transistor. The first gate electrode is disposed outside the trench and has a tip at an edge of the trench. The tip enables programming with a reduced current flow. The memory cell can be fabricated by self-aligning fabrication with an area requirement of six F2.