发明名称 Method of fabricating various-sized passivated integrated circuit chips from a borderless gate array
摘要 Effective passivation structures and guard rings can be formed in borderless gate arrays by forming the gates in an array of discrete blocks separated by thin scribe lines in which the substrate is not covered by gates. Diffusions for guard rings can be formed in the substrate for guard ring purposes, and passivation structures can be sealingly attached to the substrate. Various circuit metalizations such as discrete layers or different circuits can be produced with a single mask by covering all but a selected portion of the mask during exposure.
申请公布号 US6316334(B1) 申请公布日期 2001.11.13
申请号 US20000642394 申请日期 2000.08.18
申请人 TANNER RESEARCH, INC. 发明人 SIVILOTTI MASSIMO ANTONIO;TANNER JOHN EDWARD;LUO JIN
分类号 H01L23/544;H01L23/58;H01L27/118;(IPC1-7):H01L21/301 主分类号 H01L23/544
代理机构 代理人
主权项
地址