发明名称 Molding die for concurrently molding semiconductor chips without voids and wire weep
摘要 A molding die used for concurrently packaging semiconductor chips in a large piece of synthetic resin has a cavity rectangular in cross section and having two long peripheral lines and two short peripheral lines for accommodating a circuit panel where the semiconductor chips are mounted, melted synthetic resin is supplied through a gate extending along one of the long peripheral lines to the cavity so that the melted synthetic resin smoothly flows over the cavity, and the smooth flow prevents the molded product from voids and a wire weep.
申请公布号 US6315540(B1) 申请公布日期 2001.11.13
申请号 US20000680915 申请日期 2000.10.06
申请人 NEC CORPORATION 发明人 TSURUTA HISAYUKI
分类号 B29C45/02;B29C45/14;B29C45/26;B29C45/27;B29L31/34;H01L21/56;(IPC1-7):H01L21/56;B29L45/14 主分类号 B29C45/02
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