Integrated memory with at least two plate segments

摘要

One electrode of each storage capacitor C of the memory cells MC is connected via the associated memory transistor T to one of the bit lines BLi and another electrode is connected to one of the plate segments PLA, PLB; PLC, PLD. A control terminal of each selection transistor T is connected to one of the word lines WLi. In a normal operating mode, the potential of only one of the plate segments in each case is pulsed in the event of accesses to the memory cells MC. In a test operating mode, the potentials of both plate segments are pulsed simultaneously.