Method for making high-sheet-resistance polysilicon resistors for integrated circuits

摘要

A high-sheet-resistance polysilicon resistor for integrated circuits is achieved by using a two-layer polysilicon process. After forming FET gate electrodes and capacitor bottom electrodes from a polycide layer, a thin interpolysilicon oxide (IPO) layer is deposited to form the capacitor interelectrode dielectric. A doped polysilicon layer and an undoped polysilicon layer are deposited and patterned to form the resistor. The doped polysilicon layer is in-situ doped to minimize the temperature and voltage coefficients of resistivity. Since the undoped polysilicon layer has a very high resistance (infinite), the resistance is predominantly determined by the doped polysilicon layer. The doped polysilicon layer can be reduced in thickness (less than 1000 Angstroms) to further increase the sheet resistance for mixed-mode circuits, while the undoped polysilicon layer allows contact openings to be etched in an insulating layer over the resistor without overetching the thin doped polysilicon layer and damaging the underlying IPO layer.