POLYPHASE CLOCK SIGNAL GENERATING CIRCUIT AND SELECTING CIRCUIT

摘要

PURPOSE: A polyphase clock signal generating circuit and a selecting circuit is provided to obtain a polyphase clock signals which have desired frequencies and phase differences. CONSTITUTION: A PLL circuit(100) generates 10 phase clock signals(PHA1 to PHA10) according to a reference clock signal(REFCLK). A selecting circuit(300) has its input terminals and output terminals connected so that a clock signal having a phase difference 2ns in 10 phase clock signals(PHA1 to PHA10) is supplied to output terminals t1b to t10b. A frequency-dividing circuit(200) includes D flip-flops and NOR circuits. The D flip-flops perform frequency division after the D flip-flop which receives a clock of a last phase starts frequency division. Consequently, polyphase clock signals(PHA1 to PHA10) having desired frequencies and phase differences are obtained without adjusting a voltage-controlled oscillation circuit.