| 摘要 |
PROBLEM TO BE SOLVED: To provide a means that can directly and effectively access a fast memory which is connected one to one to an exclusive I/F from an external bus master. SOLUTION: When an external bus master 212 accesses an RDRAM 210, a DMA is set and requested to an internal DMA control part 204 by means of protocol control signals such as HLDRQ (213), HLDAK (214), MRQ (215) and MREADY (216). Meanwhile, the bus master 212 outputs the same command of protocol as that of protocol to be given when a CPU 201 gains access to the RDRAM 210 to an external system bus 211. The bus master 212 performs the DMA data transfer to the RDRAM 210 via a direct path set between a slow bus control part 206 and a fast bus control part 205.
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