发明名称 PROCEDURE FOR WORST-CASE ANALYSIS OF DISCRETE SYSTEMS
摘要 <p>A general methodology for worst-case analysis of systems with discrete observable signals is disclosed. According to one embodiment, a signature (50) is chosen and a σ-abstraction F (52) is created, based on the system and the particular property to be analyzed. This procedure requires a user to facilitate the creation of an appropriate signature and σ-abstraction (53, 54). Next, for a given length of time T (58), a signature s is determined (58). From the signature s the worst-case boundary conditions are determined (60). The methodology may also be applied to timing analysis of embedded systems implemented on a single processor. The procedure calculates a time T which is an upper bound (60) on the time a processor can be busy (i.e. busy period). Thus, for the busy-period analysis, the time T is no longer fixed. As in the first embodiment, a signature σ is selected and a σ-abstraction F is created. A workload function R is chosen, and a signature s and time T are calculated. The calculated time T is an upper bound on the length of a busy period for the given system.</p>
申请公布号 WO2001082146(A1) 申请公布日期 2001.11.01
申请号 US2001040543 申请日期 2001.04.18
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