Redundant memory cell for dynamic random access memories having twisted bit line architectures

摘要

A dynamic random access memory (DRAM) device includes a memory cell array having a twisted bit line architecture with at least one pair of redundant rows of memory cells. Redundant row decode circuitry is capable of configuring the pair of redundant rows to replace any one row of memory cells having a defect. Each pair of bit lines is coupled to a distinct memory cell from each redundant row of the redundant row pair so that both the true and complement version of a data value is maintained by the redundant row pair. Rows of reference cells are disconnected and/or disabled during a memory access operation involving the redundant row pair. <IMAGE>