发明名称 |
Architecture for a dual-bank page mode memory with redundancy |
摘要 |
A memory circuit (100) includes address circuitry (104) configured to receive address data and a plurality of I/O buffers (112). A core cell array (102) includes core cells and redundant core cells. Sense amplifiers (108) including read sense amplifiers (132) and redundant sense amplifiers may be coupled to the I/O buffers by word selection circuitry (110). Redundancy is implemented on an I/O-by-I/O basis, so that a redundant core cell and sense amplifier may be substituted for any failed bit in the core cell array.
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申请公布号 |
US6310805(B1) |
申请公布日期 |
2001.10.30 |
申请号 |
US20000676902 |
申请日期 |
2000.10.02 |
申请人 |
ADVANCED MICRO DEVICES, INC.;FUJITSU LIMITED |
发明人 |
KASA YASUSHI;SHING MING-HUEI |
分类号 |
G11C7/00;G11C29/00;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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