| 摘要 |
PROBLEM TO BE SOLVED: To provide a new improved clock circuit which is so arranged as to minimize adverse influence such as the generation of relative noise on a clock line in an integrated circuit(IC) chip. SOLUTION: This is a clock circuit on the IC chip (46) which is so adapted as to respond to the clock wave of a clock wave source (48) and connected between a 1st DC power line (90) and a 2nd DC power line (91) of the IC chip (46), and the clock circuit includes a driver (50) having 1st and 2nd outputs (80, 81) for outputting 1st and 2nd complementary clock waves in response to the clock wave of the clock wave source, a receiver which has 1st and 2nd inputs (62, 64), and 1st and 2nd clock lines (18, 20) which are connected between the 1st and 2nd outputs of the driver and the 1st and 2nd inputs of the receiver respectively. |
