| 摘要 |
<p>A semiconductor device comprising a memory cell, which memory cell comprises: a write transistor (TWR), a read transistor (TRE),- a sense transistor (TSE) provided with a sense transistor gate, a first sense transistor electrode (7) and a second sense transistor electrode (3), the first sense transistor electrode (7) being connected to a read transistor electrode (9), the sense transistor gate being arranged as a floating gate (FG), said floating gate being separated from the second sense electrode (3) by a sense transistor oxide layer (THINOX) and from a write transistor electrode (1) by a tunnel oxide layer (TUNOX); a voltage source arrangement (5, Vsi-p, Vsi-e) to provide the second sense transistor electrode (3) with a predetermined voltage during programming and erasing, such that no stress induced leakage current occurs in the sense transistor oxide layer (THINOX).</p> |
