发明名称 SEMICONDUCTOR MEMORY AND ITS TEST METHOD
摘要 PURPOSE: To provide a semiconductor memory in which an increment in pattern area is suppressed to the minimum and a BIST circuit which can obtain redundancy relieving information is realized, a fault rate of the BIST circuit itself can be reduced by using simple algorithm and its test method. CONSTITUTION: This device is provided with a memory circuit 10 having an array 11 of a normal memory cell and an array 12 of a redundancy cell, a storage element 16 for storing redundancy data consisting of non-volatile elements in which storage data can be programmed, from the outside and cannot be rewritten, a register 15 storing data of the storage elements after supplying power, a redundancy decision circuit 14 deciding whether a redundancy cell is used or not by comparing data stored in the register with an address inputted from the outside, and a redundancy data rewriting circuit 17 which can input other redundancy data again to the register from an element other than storage elements and can rewrite stored redundancy data.
申请公布号 KR20010092411(A) 申请公布日期 2001.10.24
申请号 KR20010014580 申请日期 2001.03.21
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 FUKUDA RYO
分类号 G06F12/16;G06F11/22;G11C29/00;G11C29/04;G11C29/12;G11C29/44;(IPC1-7):G11C29/00 主分类号 G06F12/16
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