发明名称 |
Clock monitor circuit and synchronous semiconductor memory device utilizing the circuit |
摘要 |
A clock monitor circuit includes a first and second delay and clock signal generating unit for receiving a clock signal and an inverted clock signal, respectively. The first and second delay and clock signal generating units generate a first and second signals, respectively. A logic sum unit logically-sums the first and second signals to generate a stop clock signal. The clock monitor circuit according to the present invention can monitor the presence of a clock signal irrespective of an operation cycle of the clock signal. Further, the synchronous semiconductor memory device utilizing the clock monitor circuit according to the present invention is adapted to consume electric current only when a clock signal is present. That is, the device does not consume electric current when the clock signal is not present thereby reducing unnecessary waste of electric power in the stand-by mode.
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申请公布号 |
US6307412(B1) |
申请公布日期 |
2001.10.23 |
申请号 |
US19990323590 |
申请日期 |
1999.06.01 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM EUN-CHEOL;KWON KOOK-HWAN |
分类号 |
G11C11/413;G06F1/04;G11C7/22;G11C11/407;H03K5/13;H03K5/15;H03K5/19;(IPC1-7):H03K5/01 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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