发明名称 Vertical structure and process for semiconductor wafer-level chip scale packages
摘要 In a semiconductor package for a chip having terminals on both sides, for example, a power MOSFET in which the gate and source terminals are on the front side and the drain terminal is on the back side, electrical contact is made with the back side terminal by extending vias, which can take the form of trenches, holes or other cavities, either entirely or patrially through the chip. The vias are filled with a metal or other electrically conductive material. The process is performed on the chips in a wafer simultaneously. The resulting package is compact and economical to manufacture and can readily be mounted, flip-chip style, on a printed circuit board.
申请公布号 AU5141801(A) 申请公布日期 2001.10.23
申请号 AU20010051418 申请日期 2001.04.06
申请人 SILICONIX, INC. 发明人 Y. MOHAMMED KASEM;YUEH-SE HO;SHAWN LUO LEE;CHANGSHENG CHEN;EDDY TJHIA;BOSCO LAN;JACEK KOREC;ANUP BHALLA
分类号 H01L29/41;H01L21/3205;H01L21/336;H01L21/768;H01L23/12;H01L23/31;H01L23/48;H01L23/52;H01L29/78 主分类号 H01L29/41
代理机构 代理人
主权项
地址