发明名称 MOS load, pole compensation
摘要 An apparatus comprising an analog circuit, a passive circuit and a first circuit. The analog circuit may be configured to vary a voltage of an output signal in response to a first signal. The passive circuit may be configured to further vary the voltage. The first circuit may be configured to further vary the voltage. The first circuit generally comprises a parasitic capacitance. The passive circuit and the first circuit are generally coupled in series.
申请公布号 US6307437(B1) 申请公布日期 2001.10.23
申请号 US20000540107 申请日期 2000.03.31
申请人 CYPRESS SEMICONDUCTOR CORP. 发明人 HENRION W. S.;KRUCZKOWSKI PHILLIP
分类号 H03F1/08;H03F3/45;(IPC1-7):H03F1/14 主分类号 H03F1/08
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