| 摘要 |
PURPOSE: A channel decoding module device for an IMT-2000 system is provided to increase decoding channel receiving capacity by simultaneously performing decoding functions to one high-speed channel and two low-speed channels such as voice and control channels. CONSTITUTION: A power supply unit(10) converts 5V power into 3.3V and 2.5V powers needed in a channel decoding module device, and provides the 3.3V and 2.5V powers. A clock generating unit(20) generates a clock needed for the operation of the channel decoding module device. An FPGA(30) performs a decoding function to two low-speed channels such as voice and control channels, generates a control signal for controlling the channel decoding module device and an address for reading/writing a DPRAM(Dual Port RAM), and performs an interface with a processor(80). A high-speed data processing unit(40) performs one high-speed channel such as video and data channels. First to third DPRAM(51-53) receive and transmit data decoded in the FPGA(30) and the high-speed data processing unit(40) and decoding data in the FPGA(30) and the high-speed data processing unit(40), and store the data. A buffer(60) performs the buffering of the decoded data or the decoding data when communicating with a processor(80).
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