发明名称 INTERCONNECT SCHEME FOR INTEGRATED CIRCUITS
摘要 <p>A novel interconnect layout method and metallization scheme is provided that simplifies the process of fabricating multilayer interconnects. The process of the present invention provides a multilevel interconnect structure formed solely from patterned metal layers stacked on top of each other. Both interconnect lines which form electrical connections along horizontal paths, as well as contacts which form electrical connections along vertical paths, can be formed using patterned metal interconnects as building-blocks. No specific process module is needed for contact layers. The use of patterned metal layers formed from the same process modules makes both design and construction of multilayer interconnects simpler. Accordingly, the manufacturing process is simplified, thus resulting in lower cost. To form thicker metal layers for the purpose of constructing thick interconnect lines, two or more patterned metal layers may be stacked on each other. In this manner, vertical low ohmic bussing is made possible.</p>
申请公布号 EP0852065(B1) 申请公布日期 2001.10.17
申请号 EP19960929801 申请日期 1996.08.30
申请人 ADVANCED MICRO DEVICES INC. 发明人 STOLMEIJER, ANDRE
分类号 H01L21/768;H01L23/522;H01L23/528;(IPC1-7):H01L21/768 主分类号 H01L21/768
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