发明名称 |
Method and structure for reducing interconnect system capacitance through enclosed voids in a dielectric layer |
摘要 |
A reduced capacitance interconnect system. A first metal layer is formed to a predetermined level above a first dielectric layer which is formed on a semiconductor substrate. The first metal layer level forms multiple interconnect lines wherein each interconnect line is separated from each adjacent interconnect line by a trench including a trench having a highest aspect ratio. A second dielectric layer is formed on the first metal layer and in the trenches between the interconnect lines such that an enclosed void having a void tip substantially level with the top of the metal layer is formed in at least each trench having an aspect ratio above a predetermined minimum aspect ratio, wherein the enclosed void in the trench having the highest aspect ratio has a void volume which is at least 15% of the volume of the trench.
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申请公布号 |
US6303464(B1) |
申请公布日期 |
2001.10.16 |
申请号 |
US19960774382 |
申请日期 |
1996.12.30 |
申请人 |
INTEL CORPORATION |
发明人 |
GAW ENG T.;VU QUAT T.;FRASER DAVID B.;CHIANG CHIEN;YOUNG IAN A.;MARIEB THOMAS N. D. |
分类号 |
H01L21/768;(IPC1-7):H01L21/76 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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