| 摘要 |
PROBLEM TO BE SOLVED: To stabilize the levels of output signals outputted from respective stages of a shift register. SOLUTION: A capacitor C1 is inserted between wiring A connected by being enclosed by the source of TFT 21, gate of TFT 22 and drain of TFT 23 and wiring for supplying a reference voltage Vss for every stage. When electric charges are not accumulated on the wiring A and the TFT 21 s turned off, the wiring A becomes floating state and when a high level clock signal CK1 or CK2 is supplied to the drain of TFT 22 at this time, the potential of the wiring A is raised by the parasitic capacitance of the TFT 22. However, this rise of potential can be relaxed by the capacitor C1, it is prevented that the gate voltage of the TFT 22 exceeds threshold voltage and the clock signal CK1 or CK2 is leaked as output signals OUT1, OUT2,.... |
