| 摘要 |
PROBLEM TO BE SOLVED: To provide a data processor capable of reducing the fan-out of a control signal for controlling a pipeline. SOLUTION: The data processor is provided with a 1st pipe line processing part 11 for executing processing divided into five stages, a 2nd pipeline processing part 22 for executing processing in a state delayed by one stage from the processing part 11 and plural flip flops(FFs) for latching control signals inputted to respective stages. Since the processing part 22 executes processing on respective stages on the basis of delayed control signals Control-A to Control- E obtained by temporarily latching control signals Control-A to control-E inputted to respective stages by respective FFs 3, the fan-out of the control signals Control-A to Control-E is reduced and the signal delay of the control signals Control-A to Control-E can be reduced. In addition, the wiring length of a control signal for transmitting the control signals Control-A to Control-E can be extended as compared with a conventional method.
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