发明名称 |
VIDEO SIGNAL PROCESSING CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To provide a video signal processing circuit for realizing the multiple screens of moving images by using a FIFO memory without degrading image quality by a passing phenomenon. SOLUTION: Field memories (FIFO memories) 2 and 3 are separately provided with a terminal IE for controlling the validity/invalidity of data input and the terminal WAE for controlling the validity/invalidity of address increase. Write area control circuits 8 and 9 write video signals to a partial area and a field signal shift circuit 10 shifts field signals FOE and generates the field signals FOE'. A passing avoiding field generation circuit 11 generates the field signals FOE" for indicating a field where the passing phenomenon is not generated by read reset signals RRST and the field signals FOE'.
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申请公布号 |
JP2001285713(A) |
申请公布日期 |
2001.10.12 |
申请号 |
JP20000090607 |
申请日期 |
2000.03.29 |
申请人 |
VICTOR CO OF JAPAN LTD |
发明人 |
IHARA AKINORI |
分类号 |
G06F5/06;G06F5/16;G09G5/14;H04N5/073;H04N5/265;H04N5/45;H04N5/66;(IPC1-7):H04N5/265 |
主分类号 |
G06F5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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