| 摘要 |
The present invention provides a video processor which has a simple circuit configuration and can scale up and down image resolution freely. A video signal processor includes a plurality of line memories, each storing one horizontal scanning line of video data series, a controller for controlling writing and reading operations of input video data series in the line memories for every horizontal scanning line, and an arithmetical unit for generating a new horizontal scanning line of video data series based on video data series from two line memories. The controller selects the vertical scaling power of the resolution, and generates a horizontal scanning synchronizing signal having a period depending on the selected scaling power. The arithmetical unit is triggered by the horizontal scanning synchronizing signal and generates a new video data series.
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