| 摘要 |
PURPOSE: A dual port static random access memory is provided to be capable of reducing bit line capacitance and signal delay on a word line. CONSTITUTION: A memory cell array is divided into two memory blocks(10, 30), and an address decoder(20) for selecting a word line is disposed between the memory blocks(10, 30). Each of the memory blocks(10, 30) has a plurality of word lines extended in a row direction, and a plurality of bit lines extended in a column direction. Signals for selecting word lines are supplied to each memory block via buffers(AB1-AB8) from the address decoder(20).
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