发明名称 |
Timing-control circuit device and clock distribution system |
摘要 |
A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin 11) is entered to a timing-control circuit (SMDF 14) and used to generate an internal clock (dclk 12), then generates an external clock (clkout 13) through a buffer (BUF 15). The external clock signal is fed back to the timing-control circuit (SMDF 14) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA 21, MCC 22) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL 24) for controlling a delay time, so that the delay circuit (DCL 24) can change the delay time according to the detected phase difference.
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申请公布号 |
US6300807(B1) |
申请公布日期 |
2001.10.09 |
申请号 |
US19990388438 |
申请日期 |
1999.09.02 |
申请人 |
HITACHI, LTD.;HITACHI ULSI SYSTEMS CO., LTD. |
发明人 |
MIYAZAKI MASAYUKI;ISHIBASHI KOICHIRO;SAKATA TAKESHI;HANZAWA SATORU;MIZUNO HIROYUKI;HASEGAWA KIYOSHI;KOKUBO MASARU;AOKI HIROKAZU |
分类号 |
G06F1/10;H03K5/135;H04L7/00;(IPC1-7):H03L7/06 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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