| 摘要 |
A system and method that prevents address aliasing and eliminates the unnecessary clock cycle consumed by the use of a dual address cycle when using a single address cycle to transmit a target address in a computer system including target devices having addresses of different sizes, such as 32-bit and 64-bit target devices, with 32-bit and 64-bit addresses, respectively. In addition, a combination of single address cycles and dual address cycles may be used to prevent address aliasing while permitting access to the entire address spaces of the target devices. The computer system includes a bus, an initiator device coupled to the bus, a first target device coupled to the bus, and a second target device coupled to the bus. The first target device has a first address range containing a plurality of bits, and the second target device has a second address range containing a fewer number of bits than the first address range. The second address range includes addresses that are specified according to a first prescribed value for a most significant bit. The first address range includes addresses that are specified according to a second prescribed value for the most significant bit to exclude the second address range such that the initiator device can transmit the first address to the first target device without aliasing the second address with the first address. The initiator device selects either the first address range or the second address range for the target address by specifying either the first prescribed value or the second prescribed value in the target address.
|
