发明名称
摘要 <p>An intelligent data bus interface using a triple-port memory having three independent data ports that provide simultaneous access to the data stored in the memory to two bi-directional data buses and to a data processor. The two data buses and the processor are coupled to separate data ports and each is able to independently access data in the triple-port memory at the full data rate of each. Because of the use of the triple-port memory, no data copying or moving is required in order to provide access to the data to the processor or the data buses. The intelligent data bus interface is particularly suitable for handling encryption/decryption, network protocol and PCI/SCI bridging at full speed at any of its ports without burdening a host processor.</p>
申请公布号 JP2001517844(A) 申请公布日期 2001.10.09
申请号 JP20000513376 申请日期 1998.09.22
申请人 发明人
分类号 G06F13/12;G06F13/00;G06F13/14;G06F13/36;G06F13/40;H04L;H04L13/08;(IPC1-7):G06F13/12 主分类号 G06F13/12
代理机构 代理人
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