| 摘要 |
PROBLEM TO BE SOLVED: To eliminate the fault that many patterns need to be inputted to initialize an LSI from a reset state to a desired state to be tested by a logic circuit test of the LSI and it takes a long time for the input. SOLUTION: A logic machine is regarded as a state transition machine and a test pattern which has a short, execution time is generated fast as a fault detection test pattern for detecting a fault place as the state transition machine having a level higher than a gate level by using genetic algorithm and applied to a logic circuit having got out of order to infer the mentioned fault place. Thus, an object area of fault place specification by gate level fault inference is narrowed down to improve the precision of the gate level fault inference and shorten the execution time. |
