Prefetch for TLB cache

摘要

A memory management unit (42) for use in a digital signal processor (30) or other processing device includes circuitry for obtaining a virtual to physical translation responsive to a prefetch command. The prefetch command can be initiated by performing a write access to a dummy register. Upon detecting the prefetch command, a TLB (60) is checked to see if the physical base address associated with a provided virtual address is currently available in the TLB (60). If not, walking table logic (78) performs a table lookup in main memory (34) to obtain the translation. The operations of the walking table logic (78) are performed without blocking continued operations by the DSP core (36). <IMAGE>