| 摘要 |
PROBLEM TO BE SOLVED: To easily operate a circuit at high speed by making a phase difference from a synchronous clock source smaller and a phase fluctuation smaller at the time of HOLDOVER when a time of HOLDOVER becomes long with respect to digital data sampled at the time of normal state. SOLUTION: In a phase holding method for holding a synchronous source clock of a synchronous digital hierarchy(SDH) device, digital data that sample the synchronous source clock signal at the time of normal state are stored in a storage means, the digital data of the storage means are selected when the clock cutoff is detected, and an oscillation pulse of a voltage control oscillator 11 is generated. Also, in the phase holding method, the digital data of the storage means are added and subtracted by data obtained by phase comparing the synchronous source clock signal with the oscillation pulse of the voltage control oscillator 11. |
