发明名称 WRITE CACHE CIRCUIT, RECORDER WITH WRITE CACHE CIRCUIT AND WRITE CACHE METHOD
摘要 PROBLEM TO BE SOLVED: To provide a write cache circuit capable of enhancing use efficiency of a memory and to provide, a recorder with the circuit and a write cache method. SOLUTION: User data to be transmitted from the host side is preliminarily stored in write cache areas A1 to Am of an SDRAM 12 by unit of error correction processing. ECC/EDC encode processing to add redundant data such as an error correction code to the stored user data by unit of error correction processing is performed by using encode areas B1 or B2 of the SDRAM 12. Pieces of the data to which the ECC/EDC encoder processings are applied are successively read from the area B1 or B2 and written in a disk after subjected to modulation.
申请公布号 JP2001265533(A) 申请公布日期 2001.09.28
申请号 JP20000076233 申请日期 2000.03.17
申请人 SANYO ELECTRIC CO LTD 发明人 FUMA MASATO;OKAMOTO SANEYUKI
分类号 G06F12/08;G06F3/06;G06F12/16;G11B20/10;G11B20/18;G11B27/19;G11B27/24;G11B27/30 主分类号 G06F12/08
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