| 摘要 |
<p>A method and apparatus for synchronizing a bus bridge to a master clock comprising receiving (1110) a time stamp packet at an input clock register of the bus bridge, comparing (1115) the value of the input clock register to the value of an output clock register of the bus bridge, obtaining (1120, 1125) an error value of the output clock register from the comparison, and determining (1130) whether the error value is below a predetermined threshold are described.</p> |
