| 摘要 |
PURPOSE: A method for manufacturing a storage node of a memory cell capacitor is provided to improve a refresh characteristic of the capacitor and sensitivity of a sense amplifier, by maximizing the area of the storage node in a limited area. CONSTITUTION: The first gate, the first insulation layer, the first planarization layer, a cell plug(26), the first interlayer dielectric(27) and a bitline(28) are sequentially formed on a semiconductor substrate(21) having an isolation region(22) by a conventional process. The first nitride layer(29) and the second interlayer dielectric(30) are formed on the entire surface of the resultant structure. The second nitride layer(31) and the first oxide layer are formed on the second interlayer dielectric. The insulation layers are selectively etched to expose the cell plug through a photolithography process. The first polysilicon(33) is deposited and planarized to form a node contact. The second oxide layer is formed on the entire surface of the resultant structure. The second and first oxide layers and the second nitride layer are selectively etched through a photolithography process. The second interlayer dielectric is partially exposed to make the node contact protruded in the center. The second polysilicon(35) is deposited on the entire surface, and the third oxide layer is deposited to fill the etched region. The third oxide layer and the second polysilicon are planarized until the second oxide layer is exposed, and the third, second and first oxide layers are removed. A hemispheric grain(HSG) layer(37) is formed on the remaining second polysilicon.
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