发明名称 |
DEVICE VERIFICATION SYSTEM ON LOOP CONNECTION BY INPUT/ OUTPUT DEVICE SIMULATOR |
摘要 |
PROBLEM TO BE SOLVED: To surely verify the operations and detailed protocols on a loop of an input/output processor by using a single input/output device simulator under the environment of being loop-connected with plural input/output devices. SOLUTION: For the verification of the operations and the protocols on the loop of the input/output processor loop-connected with the plural input/ output devices, the single input/output device simulator and the input/output processor are connected one to one. In the constitution, plural port addresses are logically allocated by the single input/output device simulator, control data to the respective port addresses are transferred and thus, pseudo verification is enabled under the constitution where the input/output devices and the input/ output device simulator are present in large scale loop constitution. |
申请公布号 |
JP2001256121(A) |
申请公布日期 |
2001.09.21 |
申请号 |
JP20000071005 |
申请日期 |
2000.03.09 |
申请人 |
HITACHI LTD;HITACHI INFORMATION TECHNOLOGY CO LTD |
发明人 |
KATAKURA TOMOHIRO;KAWAGUCHI HIROYUKI;ISODA HIDEO |
分类号 |
G06F13/14;G06F11/22;G06F11/28;G06F13/00 |
主分类号 |
G06F13/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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