| 摘要 |
PROBLEM TO BE SOLVED: To reduce the capacitance fluctuation of a PIN diode at zero-bias time regardless of the fluctuation of the resistivity of the i-layer of a pin junction. SOLUTION: In a method of manufacturing diode, a main pin junction 3a sandwiching the i-layer 2b between an n-type high-concentration substrate 1 and a p-type diffusion layer 3 is formed by growing an epitaxial layer which is formed for forming the intrinsic semiconductor layer (i-layer 2b) of the PIN diode on the substrate 1, and forming the diffusion layer 3 on the surface of the epitaxial layer 2. A channel stopper layer 4 which surrounds the pin junction 3a is formed to meet the relation of W1<=D (where, W1 is the widths of the junction 3a and channel stopper layer 4 and D is the width of the i-layer 2b) and the relation of D1>D (where, D1 is the thickness of the stopper layer 4). Because of this structure, the extent of a depletion layer at zero-bias time is limited by the effective area, which varies depending upon a chip structure, on the inside of the stopper layer 4 and can limit the capacitance fluctuation of the PIN diode even when the resistivity of the high-resistance i-layer 2b fluctuates.
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