METHOD AND APPARATUS FOR VERIFICATION OF VALIDITY OF TEST PATTERN

摘要

PROBLEM TO BE SOLVED: To provide a method and an apparatus in which whether a test pattern generated from CAD data in proper or not is verified without using an LSI tester. SOLUTION: The test pattern which is output from an LSI tester simulator 10 and its test cycle number are stored in a first memory 26. Device output data which is constituted of the CAD data and its test time are stored in a second memory 27. The device output data in the second memory corresponding to the test pattern in the first memory is extracted by a comparison synchronization part 28 so as to be input to the simulator 10. In the simulator 10, the device output data is compared with an expected value. When all agree, the test pattern is judged to be proper. Whether strobe pulses which prescribe the judgment timing of the device output data and that of the expected value are generated or not with reference to all states of the device output data is verified.