| 摘要 |
The reference voltage generation device uses reference cells (R1T,R2T ; R1C,R2C) within the ferroelectric memory provided with a logic "0" and a logic "1", at the ends of the word lines (WLT,WLC) along a reference bit line (BLTREF1, BLTREF2 ; BLCREF1,BLCREF2). The ferroelectric memory may be provided via a MOS technology, with a pulsed plate parallel to the bit line for providing a selective-read memory, with a reference or dummy cell at the end of each word line.
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