发明名称 |
Programmable logic array integrated circuit architectures |
摘要 |
A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate "lonely register" function in modules of the regions.
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申请公布号 |
US2001022519(A1) |
申请公布日期 |
2001.09.20 |
申请号 |
US20010865227 |
申请日期 |
2001.05.25 |
申请人 |
ALTERA CORPORATION |
发明人 |
CLIFF RICHARD G.;HEILE FRANCIS B.;HUANG JOSEPH;LANE CHRISTOPHER F.;LEE FUNG FUNG;MCCLINTOCK CAMERON;MENDEL DAVID W.;NGO NINH D.;PEDERSEN BRUCE B.;REDDY SRINIVAS T.;SUNG CHIAKANG;VEENSTRA KERRY;WANG BONNIE I. |
分类号 |
H03K19/173;H03K19/177;(IPC1-7):H03K19/177 |
主分类号 |
H03K19/173 |
代理机构 |
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