| 摘要 |
A ferroelectric non-volatile memory (100, 436) comprising: a plurality of memory cells (14, 116, 117, 118, 119), each containing an FeFET (40, 140A) and a MOSFET (20, 120A), each of said FeFETs (14) having a source (42), a drain (44), a substrate (45), and a gate (58), and each MOSFET (20) having a pair of source/drains (22, 23) and a gate (21). The cells are arranged in an array comprising a plurality of rows (180) and a plurality of columns (184). A gate line (132) and a bit line (134) are associated with each column, and a word line (136), a drain line (139), and a substrate line (138) are associated with each row. A read MOSFET (160) is connected between a drain input (137) and the drain line associated with each row. The gate (165) of the read MOSFET is connected to an input for the read enable signal.
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