| 摘要 |
An automatic equalizer comprises a transmission symbol sequence generation circuit 101, a parallel received signal estimation circuit 102, subtracters 103-1 through 103-6, absolute value squaring arithmetic circuits 104-1 through 104-6, adders 105-1 through 105-4, and a discriminator 106. Maximum likelihood estimation can be performed with simple operations by means of using added error signals given by adding square error signals obtained from estimated error signals for an N number of delayed received signals delayed by a time instant corresponding to 0 through (N-1) symbols, to select the transmission symbol sequence having the smallest error.
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