Electroless plated semiconductor vias and channels

摘要

A method of manufacturing a semiconductor device is provided in which a semiconductor substrate with a dielectric layer has channel and via openings formed in the dielectric layer. A seed layer is formed over the dielectric layer and in the openings followed by a resist over the seed layer. The resist is then removed outside the openings. The seed layer outside the openings, which is not covered by the resist, is removed and the seed layer in the openings remains intact because of the resist in the openings. The resist inside the openings is removed and the seed layer inside the openings is electroless plated to fill the openings and form the channels and vias for interconnecting the semiconductor device.