发明名称 Apparatus and method of reducing the pre-charge time of bit lines in a random access memory
摘要 According to the first embodiment of the present invention, a pre-charge device is connected to the middle of each complementary bit line. Thus, once activated, the pre-charge device only drives a load equal to half of the RC impedance of the entire bit lines during the pre-charging operation. According to the second embodiment of the present invention, a first pre-charge device is connected to one end of each complementary bit lines and a second pre-charge device is connected approximately to the middle of each complementary bit lines. Once both devices are activated, each device drives a load equal to half of the RC impedance of the entire bit lines, thus reducing the pre-charge time of the bit lines.
申请公布号 US6292416(B1) 申请公布日期 2001.09.18
申请号 US19980025290 申请日期 1998.02.11
申请人 ALLIANCE SEMICONDUCTOR CORPORATION 发明人 REDDY CHITRANJAN N.;KENGERI SUBRAMANI
分类号 G11C7/12;G11C11/4094;(IPC1-7):G11C7/00 主分类号 G11C7/12
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