发明名称 |
Scalar hardware for performing SIMD operations |
摘要 |
A system for processing SIMD operands in a packed data format includes a scalar FMAC and a vector FMAC coupled to a register file through an operand delivery module. For vector operations, the operand delivery module bit steers a SIMD operand of the packed operand into an unpacked operand for processing by the first execution unit. Another SIMD operand is processed by the vector execution unit.
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申请公布号 |
US6292886(B1) |
申请公布日期 |
2001.09.18 |
申请号 |
US19980169865 |
申请日期 |
1998.10.12 |
申请人 |
INTEL CORPORATION |
发明人 |
MAKINENI SIVAKUMAR;KIMN SUNNHYUK;DOSHI GAUTAM B.;GOLLIVER ROGER A. |
分类号 |
G06F9/302;G06F9/38;(IPC1-7):G06F17/16 |
主分类号 |
G06F9/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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