| 摘要 |
PURPOSE:To provide the circuit and method for efficient multiplication considering carry by using a multiplier with the small number of digits in the case of dividing and calculating the large number of digits in the multiplication circuit. CONSTITUTION:In the circuit to multiply an integer A of (n) bits and an integer B of (hXm) bits while defining (h), (m) and (n) as positive integers, the (h) pieces of arithmetic elements composed of the multipliers of 1Xm bits, the full adders of (m) bits and the registers of (m+2) bits are provided corresponding to the (m) bits of the integer B, and the (m) bits of the integer B are multiplied to every one bits of the integer A and outputted to the (m) bit full adders. The full adders add the outputs of the respective multipliers, the high-order 3 bits of the (m) bit full adders at the low-order digit in the case of the last clock from the register at the low-order digit, and feedback value shifting the low-order m-1 bits of the added result at the full adders in the case of the last clock from the same register to the high-order digit by one digit and supplies the high-order 3 bits to the low-order 3 bits of the full adder at the high- order digit, and the content of the m+2 bit register (n) clock later is defined as a multiplied result A.B. |
