发明名称 |
IMAGE DECODER AND IMAGE CODER |
摘要 |
<p>PROBLEM TO BE SOLVED: To apply a high-speed decoding processing to a bit stream corresponding to objects such as images that are compression-coded by the MPEG 4 system and to minimize the cost of a hardware circuit conducting the decoding processing. SOLUTION: A decoding LSI in compliance with the MPEG 4 is provided with a supplement means that applies supplement processing to decoded texture data, an arithmetic decoding means that applies arithmetic decoding processing to coded shape data and a composition means that composites the texture data to generate composite image data. The supplement means, the arithmetic decoding means and the composition means are respectively composed of a hardware circuit (exclusive engine), an arithmetic decoding engine 12, a padding engine 13 and a composition engine 14.</p> |
申请公布号 |
JP2001251625(A) |
申请公布日期 |
2001.09.14 |
申请号 |
JP20000398646 |
申请日期 |
2000.12.27 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
TAKAHASHI TOSHIYA;TOIDA HIROAKI |
分类号 |
H04N19/60;H03M7/40;H04N19/132;H04N19/134;H04N19/196;H04N19/20;H04N19/42;H04N19/423;H04N19/436;H04N19/44;H04N19/59;H04N19/91;(IPC1-7):H04N7/30 |
主分类号 |
H04N19/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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