| 摘要 |
<p>A data clock recovery circuit (3) comprises a controllable quadrature clock oscillator (6) operating at half the data rate of data input to said circuit, and a phase detector logic (7) having detector inputs coupled to the data input and having a detector output coupled to a frequency control input of the quadrature clock oscillator. The data clock recovery circuit further comprises a parallel arrangement of sampling devices, (5-1, 5-2, 5-3, 5-4) in particular flip-flops each having a clock input (CR) which is coupled to the controllable quadrature clock oscillator, a data input for the data input (D) to said circuit, and a data output coupled to the phase detector. Accurate control of the phase of recovered data is possible with the present circuit, which is easy to integrate on a limited chip area and in a low power consuming way.</p> |
