| 摘要 |
A frequency synthesizer type receiver requiring small power consumption and maintaining excellent receiving performance. In the frequency synthesizer type receiver, a reception frequency thereof is set based on an oscillatory output of a PLL circuit. When the oscillation frequency of the PLL circuit is stabilized, a control voltage can be supplied to a voltage-controlled oscillator in the PLL circuit from a controller situated outside of the PLL circuit. The tuned state of a reception unit is measured at this time. If a shift in the reception frequency is detected based on the measured value, the control voltage to be supplied to the voltage-controlled oscillator is corrected.
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