POWER MANAGEMENT FOR A MICROCONTROLLER

摘要

A power management architecture for a microcontroller. The power management architecture includes a power management state machine (130) for controlling the power mode of the central processing unit (CPU) and each of the subsystems within the microcontroller. The power management state machine (130) includes a software configurable register (SFR) (62) to enable the state machine to be configured for device and application specific applications. Each of the microcontroller subsystems is connected to the system by way of a configurable peripheral interface (FPI) (24). Each FPI includes a software configuration register (SFR) which can be configured by an operating system or application program. The SFR for the various FPIs enables the response to each of the power modes of each microcontroller subsystem to be pre-configured; thus enabling each subsystem to be independently controlled of the power management state machine (130) in order to optimize the power management of the various subsystems. Each of the FPI interfaces as well as the power management state SFR are connected to an FPI bus (24) which interconnects the FPI interfaces with the central processing unit (CPU) (22) and power management state machine SFR. The FPI bus (24) enables reads and writes of the power management state machine SFR and peripheral interface SFRs. Such a configuration allows subsystems to be added or deleted without changing the basic architecture of the power management system, thus forming a modular power management architecture which reduces the cost and complexity designing and developing the microcontrollers.