| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock generating circuit wherein the number of wiring on a back wiring board is reduced and the number of a frequency synchronism oscillator circuits is reduced as well. SOLUTION: Concerning the clock generating circuit for supplying a synchronizing clock signal through the back wiring board to plural packages accommodated on the back wiring board, this circuit is provided with at least one frequency synchronism oscillator circuit to become the common multiple of even multiples of various frequencies required for the package of the clock supply destination and a clock frequency over the back wiring board is equal to or lower than 10 MHz. Thus, concerning this clock generating circuit, the number of wiring assigned onto the back wiring board can be reduced and the number of frequency synchronism oscillator circuits in the clock generating package can be reduced. |
