Cache address conflict device without storage buffer for computer systems, has plane of multi-level/plane structure provided with a queue for holding entries of address information for data access

摘要

To extend the capability of conventional caches beyond being able to handle only a limited number of requests simultaneously as a result of the serial structure of these conventional caches, a multi-level/plane structure is used for memory access requests to be carried out, and is configured in order that the several planes/levels can receive several memory access requests, which are then parallel-processed. A plane or level of the multi-plane/level structure has a queue for holding entries of address information for data access and includes a conflict logic for testing each access request with regard to the entries of the queue for conflicts before insertion of each access request into the queue. An output logic decides which entries are to be outputted from the waiting queue as based on the results of the conflict logic.